In part 1, the 16 bit word SRAM is interfaced to the 32 bit bus bridge. Which bus bridge address bits should be connected to the SRAM_ADDR[19:1]? (Note the low order bit of SRAM_ADDR has been deliberately left out here).Question 3Select one:a.address[20:2]b.address[19:2]c.address[18:0]d.address[19:1]e.address[18:1]
Question
In part 1, the 16 bit word SRAM is interfaced to the 32 bit bus bridge. Which bus bridge address bits should be connected to the SRAM_ADDR[19:1]? (Note the low order bit of SRAM_ADDR has been deliberately left out here).Question 3Select one:a.address[20:2]b.address[19:2]c.address[18:0]d.address[19:1]e.address[18:1]
Solution
The correct answer is d. address[19:1].
Here's why:
The SRAM_ADDR[19:1] implies that there are 19 address lines for the SRAM. This means that the SRAM can address 2^19 or 524,288 locations.
The 32-bit bus bridge address bits that should be connected to the SRAM_ADDR[19:1] should also be able to address the same number of locations.
Option d. address[19:1] also has 19 address lines, which means it can also address 2^19 or 524,288 locations.
Therefore, to interface the 16-bit word SRAM to the 32-bit bus bridge, the address[19:1] of the bus bridge should be connected to the SRAM_ADDR[19:1].
The other options either have too many or too few address lines to correctly interface with the SRAM_ADDR[19:1].
Similar Questions
What should be connected to the low order bit of SRAM_ADDR in part 1?Question 4Select one:a.byte_enable[2] should be used.b.byte_enable[3] should be used.c.byte_enable[0] should be used.d.The stage state variable can be used, since in the first clock cycle this bit is 0 and in the second clock cycle it is 1.e.Address bit 0 from the bus bridge should be used for SRAM_ADDR[0]f.byte_enable[1] should be used.
With a 2 Mbyte address range and four 16 bit registers to map to this address range in part 1, select the valid approach(es) for this lab. Question 4Select one or more:a.Since the bus bridge is half word aligned, we can choose any 2 address lines apart from address[0] to determine which of the four registers is read or written to.b.Since the bus bridge is word aligned, address[1:0] is a valid choice for determining which of the four registers is read or written to.c.The address[20:17] bits form one of many minimal sets for determining which of the four registers is read or written to.d.We could choose to decode the address[10:9] bits to determine which of the four registers is chosen, even though it might be confusing.
In this lab, why are the bottom 2 bits of the address lines from the bus bridge always zero?Question 2Select one:a.The bus bridge has been configured for a data width of 32 bits, and memory is halfword addressed.b.The bus bridge has been configured for a data width of 32 bits, and memory is word aligned.c.Trick question! The bottom 2 bits of the address lines from the bus bridge are NOT always zero.d.The bus bridge has been configured for a data width of 16 bits, and memory is word aligned.
In part 3 the SRAM_Controller and Peripheral_on_External_Bus modules are not altered from parts 1 and 2, but instantiated. The instantiation of the Peripheral_on_External_Bus bus_enable signal involves the use of the bridge bus_enable ANDed with address[??]. Fill in the ?? below:
A 16-bit address bus is carrying the address4567H and is partially decoded with lines A15and A13 being unused Which one of theseaddresses would access a different hardwarelocation:• (a) E567H.• (b) 4567H.• (c) 6567H.• (d) 8567H.
Upgrade your grade with Knowee
Get personalized homework help. Review tough concepts in more detail, or go deeper into your topic by exploring other relevant questions.