What should be connected to the low order bit of SRAM_ADDR in part 1?Question 4Select one:a.byte_enable[2] should be used.b.byte_enable[3] should be used.c.byte_enable[0] should be used.d.The stage state variable can be used, since in the first clock cycle this bit is 0 and in the second clock cycle it is 1.e.Address bit 0 from the bus bridge should be used for SRAM_ADDR[0]f.byte_enable[1] should be used.

In part 1, the 16 bit word SRAM is interfaced to the 32 bit bus bridge. Which bus bridge address bits should be connected to the SRAM_ADDR[19:1]?  (Note the low order bit of SRAM_ADDR has been deliberately left out here).Question 3Select one:a.address[20:2]b.address[19:2]c.address[18:0]d.address[19:1]e.address[18:1]

What signals does the SRAM_UB_N depend on in the SRAM_Controller module? Question 6Select one: a. stage state variable, byte_enable[2], byte_enable[1] b. stage state variable, byte_enable[3], byte_enable[1] c. stage state variable, byte_enable[3], byte_enable[2] d. byte_enable[2], byte_enable[0] e. byte_enable[3], byte_enable[0]

In part 3 the SRAM_Controller and Peripheral_on_External_Bus modules are not altered from parts 1 and 2, but instantiated. The instantiation of the Peripheral_on_External_Bus bus_enable signal involves the use of the bridge bus_enable ANDed with address[??]. Fill in the ?? below:

During the SRAM write cycle all outputs of the SRAM_Controller module to the SRAM are a combinational logic function made up of one or more of the bus bridge signals: bus_enable, rw, address and byte_enable.Question 3Select one:TrueFalse

The SRAM_DQ signals are inout type. When should the SRAM_Controller tristate these signals?Question 5Select one:a.When rw=1 and bus_enable=0b.When rw=1 or bus_enable=0c.When rw=1 and bus_enable=1d.When rw=1 or bus_enable=1e.When rw=0 or bus_enable=0