<§2.11> Write the MIPS assembly code to implement the following Ccode:lock(lk);shvar=max(shvar,x);unlock(lk);Assume that the address of the lk variable is in $a0, the address of the shvarvariable is in $a1, and the value of variable x is in $a2. Your critical section shouldnot contain any function calls. Use ll/sc instructions to implement the lock()operation, and the unlock() operation is simply an ordinary store instruction.
Question
<§2.11> Write the MIPS assembly code to implement the following Ccode:lock(lk);shvar=max(shvar,x);unlock(lk);Assume that the address of the lk variable is in a1, and the value of variable x is in $a2. Your critical section shouldnot contain any function calls. Use ll/sc instructions to implement the lock()operation, and the unlock() operation is simply an ordinary store instruction.
Solution
Here is the MIPS assembly code for the given C code:
# lock(lk)
1: ll $t0, 0($a0) # load linked
bnez $t0, 1b # if $t0 != 0 (locked), try again
li $t1, 1
sc $t1, 0($a0) # store conditional
beqz $t1, 1b # if $t1 == 0 (failed to lock), try again
# shvar = max(shvar, x)
lw $t2, 0($a1) # load shvar
slt $t3, $t2, $a2 # set $t3 to 1 if shvar < x
beqz $t3, 2f # if shvar >= x, skip next instruction
sw $a2, 0($a1) # store x in shvar
# unlock(lk)
2: sw $zero, 0($a0) # unlock
This code first locks the variable lk using a loop with load linked (ll) and store conditional (sc) instructions. Then it compares shvar and x and stores the maximum of the two in shvar. Finally, it unlocks lk by storing 0 in it.
Similar Questions
Translate the following C code to MIPS assembly code. Assume that the values of a, b, i, and j are in registers $s0, $s1, $t0, and $t1, respectively. Also, assume that register $s2 holds the base address of the array D and its value is 0x10 (1016). Thus, D[j] contains the value at address 0x10 + 4 * j.for(i=0; i<a; i++)for(j=0; j<b; j++)D[j] = i + j;
For the following C statement, what is the correspondingMIPS assembly code? Assume that the variables f, g, h, i, and j are assigned toregisters $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base addressof the arrays A and B are in registers $s6 and $s7, respectively.B[8] = A[i−j];2.4 [5] <§§2.2, 2.3> For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j are assignedto registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base addressof the arrays A and B are in registers $s6 and $s7, respectively.sll $t0, $s0, 2 # $t0 = f * 4add $t0, $s6, $t0 # $t0 = &A[f]sll $t1, $s1, 2 # $t1 = g * 4add $t1, $s7, $t1 # $t1 = &B[g]lw $s0, 0($t0) # f = A[f]addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)2.5 [5] <§§2.2, 2.3> For the MIPS assembly instructions in Exercise 2.4, rewritethe assembly code to minimize the number if MIPS instructions (if possible)needed to carry out the same function.2.6 The table below shows 32-bit values of an array stored in memory.Address Data24 238 432 336 640 1
Every MIPS instruction can be implemented in at most
Translate the following MIPS instructions to binary code 1. addi $s1, $s2,5 2. addu $t1, $s3, $s4 3. xori $s1, $s2,8 4. addiu $s6,$s7,-2 5. lui $s4,1
Every MIPS instruction can be implemented in at most ans. 4 clock cycles 3 clock cycles 5 clock cycles 2 clock cycles
Upgrade your grade with Knowee
Get personalized homework help. Review tough concepts in more detail, or go deeper into your topic by exploring other relevant questions.