During a read transaction on the bus, two bits of the byte_enable[1:0] signals are required in Part 1 for assigning the read_data[15:0] signals in a bus interface.Question 8Select one:TrueFalse

In the lab the data bus is 32 bits wide. As a consequence what is the width (ie number of signals) of the byte_enable?  Your answer must be a single digit number.

A bus is a pathway for bits representing data and instructions.Group startsTrue or FalseTrue, unselectedFalse, unselected

What should be connected to the low order bit of SRAM_ADDR in part 1?Question 4Select one:a.byte_enable[2] should be used.b.byte_enable[3] should be used.c.byte_enable[0] should be used.d.The stage state variable can be used, since in the first clock cycle this bit is 0 and in the second clock cycle it is 1.e.Address bit 0 from the bus bridge should be used for SRAM_ADDR[0]f.byte_enable[1] should be used.

During a write cycle in the lab experiment, the byte_enable[1:0] signals are irrelevant for determining which bits of the register are overwritten.Question 2Select one:TrueFalse

Suppose the instruction stbio r3, 0(r2) is issued and r2 contains 0x00000011 (ie 10001 in binary)What do you expect to see on byte_enable[1:0]? Your answer should contain two digits and no spaces.