Table of LC-3 Instructions:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEMANTICSNOT 1 0 0 1 DST SRC 1 1 1 1 1 1 R[DST] ← NOT(R[SRC])ADD 0 0 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] + R[SRC2]AND 0 1 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] & R[SRC2]ADD 0 0 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] + SEXT(Immediate)AND 0 1 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] & SEXT(Immediate)LDR 0 1 1 0 DST BASE Offset R[DST] ← M[R[BASE]+SEXT(Offset)]STR 0 1 1 1 SRC BASE Offset M[R[BASE]+SEXT(Offset)] ← R[SRC]LD 0 0 1 0 DST PC Offset R[DST] ← M[inc(PC)+SEXT(PCOffset)]ST 0 0 1 1 SRC PC Offset M[inc(PC)+SEXT(PCOffset)] ← R[SRC]LDI 1 0 1 0 DST PC Offset R[DST] ← M[M[inc(PC)+SEXT(PCOffset)]]STI 1 0 1 1 SRC PC Offset M[M[inc(PC)+SEXT(PCOffset)]] ← R[SRC]LEA 1 1 1 0 DST PC Offset R[DST] ← inc(PC)+SEXT(PCOffset)BR 0 0 0 0 N Z P PC Offset PC ← inc(PC)+SEXT(PCOffset) if condition is trueelse PC ← inc(PC), see Note 3 below.JMP 1 1 0 0 0 0 0 BASE 0 0 0 0 0 0 PC ← R[BASE]TRAP 1 1 1 1 0 0 0 0 Trap Vector jump to trap vector, see Note 4 below.UNUSED 1 1 0 1 invalid instructionNotes:BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]Immediate (5), Offset (6), PC Offset (9) are N-bit 2's complement integers, where N is given in ()'sCondition Codesare set by ADD, AND, NOT, LD, LDR, LDI, LEAare used by BR based on the most recent instruction to set CCTrap Vector is an 8-bit value that is used to call an OS service routine:0x21 output a character0x23 input a character0x25 halt the program Flag question: Question 1Question 18 ptsAssume the following shows the initial contents of the specified registers:REGISTER CONTENTSR1 0000 0000 0000 1001R2 0000 0000 0000 0101R3 0000 0000 0000 0010Also assume the following LC-3 machine instructions are loaded into memory at addresses shown:0x4000 1001 001 011 1 111110x4001 0001 001 001 1 000010x4002 0001 011 010 0 00 0010x4003 0000 001 001010000After the code above completes execution, what is the final value in each register below?(Enter your 16-bit answer in hex like the following example: 0x2A3F)A.) R1? B.) R2? C.) R3? D.) PC?
Question
Table of LC-3 Instructions:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEMANTICSNOT 1 0 0 1 DST SRC 1 1 1 1 1 1 R[DST] ← NOT(R[SRC])ADD 0 0 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] + R[SRC2]AND 0 1 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] & R[SRC2]ADD 0 0 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] + SEXT(Immediate)AND 0 1 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] & SEXT(Immediate)LDR 0 1 1 0 DST BASE Offset R[DST] ← M[R[BASE]+SEXT(Offset)]STR 0 1 1 1 SRC BASE Offset M[R[BASE]+SEXT(Offset)] ← R[SRC]LD 0 0 1 0 DST PC Offset R[DST] ← M[inc(PC)+SEXT(PCOffset)]ST 0 0 1 1 SRC PC Offset M[inc(PC)+SEXT(PCOffset)] ← R[SRC]LDI 1 0 1 0 DST PC Offset R[DST] ← M[M[inc(PC)+SEXT(PCOffset)]]STI 1 0 1 1 SRC PC Offset M[M[inc(PC)+SEXT(PCOffset)]] ← R[SRC]LEA 1 1 1 0 DST PC Offset R[DST] ← inc(PC)+SEXT(PCOffset)BR 0 0 0 0 N Z P PC Offset PC ← inc(PC)+SEXT(PCOffset) if condition is trueelse PC ← inc(PC), see Note 3 below.JMP 1 1 0 0 0 0 0 BASE 0 0 0 0 0 0 PC ← R[BASE]TRAP 1 1 1 1 0 0 0 0 Trap Vector jump to trap vector, see Note 4 below.UNUSED 1 1 0 1 invalid instructionNotes:BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]Immediate (5), Offset (6), PC Offset (9) are N-bit 2's complement integers, where N is given in ()'sCondition Codesare set by ADD, AND, NOT, LD, LDR, LDI, LEAare used by BR based on the most recent instruction to set CCTrap Vector is an 8-bit value that is used to call an OS service routine:0x21 output a character0x23 input a character0x25 halt the program Flag question: Question 1Question 18 ptsAssume the following shows the initial contents of the specified registers:REGISTER CONTENTSR1 0000 0000 0000 1001R2 0000 0000 0000 0101R3 0000 0000 0000 0010Also assume the following LC-3 machine instructions are loaded into memory at addresses shown:0x4000 1001 001 011 1 111110x4001 0001 001 001 1 000010x4002 0001 011 010 0 00 0010x4003 0000 001 001010000After the code above completes execution, what is the final value in each register below?(Enter your 16-bit answer in hex like the following example: 0x2A3F)A.) R1? B.) R2? C.) R3? D.) PC?
Solution
The LC-3 machine instructions provided are as follows:
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NOT R1, R3: This instruction performs a bitwise NOT operation on the contents of R3 and stores the result in R1. The initial value of R3 is 0x0002, and the bitwise NOT of this value is 0xFFFD.
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ADD R1, R1, #2: This instruction adds the immediate value 2 to the contents of R1 and stores the result back in R1. The initial value of R1 after the NOT operation is 0xFFFD, so adding 2 gives us 0xFFFF.
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ADD R3, R2, R2: This instruction adds the contents of R2 to itself and stores the result in R3. The initial value of R2 is 0x0005, so adding this to itself gives us 0x000A.
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BRzp R1: This instruction is a conditional branch that is taken if the Zero or Positive condition codes are set. Since the last operation resulted in a negative value in R1, this branch is not taken and the PC is incremented normally.
So, the final values in the registers are:
A.) R1 = 0xFFFF B.) R2 = 0x0005 (unchanged) C.) R3 = 0x000A D.) PC = 0x4004 (incremented by 4 as there are 4 instructions)
Similar Questions
Table of LC-3 Instructions:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEMANTICSNOT 1 0 0 1 DST SRC 1 1 1 1 1 1 R[DST] ← NOT(R[SRC])ADD 0 0 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] + R[SRC2]AND 0 1 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] & R[SRC2]ADD 0 0 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] + SEXT(Immediate)AND 0 1 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] & SEXT(Immediate)LDR 0 1 1 0 DST BASE Offset R[DST] ← M[R[BASE]+SEXT(Offset)]STR 0 1 1 1 SRC BASE Offset M[R[BASE]+SEXT(Offset)] ← R[SRC]LD 0 0 1 0 DST PC Offset R[DST] ← M[inc(PC)+SEXT(PCOffset)]ST 0 0 1 1 SRC PC Offset M[inc(PC)+SEXT(PCOffset)] ← R[SRC]LDI 1 0 1 0 DST PC Offset R[DST] ← M[M[inc(PC)+SEXT(PCOffset)]]STI 1 0 1 1 SRC PC Offset M[M[inc(PC)+SEXT(PCOffset)]] ← R[SRC]LEA 1 1 1 0 DST PC Offset R[DST] ← inc(PC)+SEXT(PCOffset)BR 0 0 0 0 N Z P PC Offset PC ← inc(PC)+SEXT(PCOffset) if condition is trueelse PC ← inc(PC), see Note 3 below.JMP 1 1 0 0 0 0 0 BASE 0 0 0 0 0 0 PC ← R[BASE]TRAP 1 1 1 1 0 0 0 0 Trap Vector jump to trap vector, see Note 4 below.UNUSED 1 1 0 1 invalid instructionNotes:BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]Immediate (5), Offset (6), PC Offset (9) are N-bit 2's complement integers, where N is given in ()'sCondition Codesare set by ADD, AND, NOT, LD, LDR, LDI, LEAare used by BR based on the most recent instruction to set CCTrap Vector is an 8-bit value that is used to call an OS service routine:0x21 output a character0x23 input a character0x25 halt the program Flag question: Question 1Question 18 ptsAssume the following shows the initial contents of the specified registers:REGISTER CONTENTSR1 0000 0000 0000 1001R2 0000 0000 0000 0101R3 0000 0000 0000 0010Also assume the following LC-3 machine instructions are loaded into memory at addresses shown:0x4000 1001 001 011 1 111110x4001 0001 001 001 1 000010x4002 0001 011 010 0 00 0010x4003 0000 001 001010000After the code above completes execution, what is the final value in each register below?(Enter your 16-bit answer in hex like the following example: 0x2A3F)A.) R1? B.) R2? C.) R3? D.) PC?
Classify each of the following LC-3 instructions shown in hex:A.) 0x6AE3 B.) 0x02AA C.) 0x50E9 D.) 0xF025
Select where the source operands are located for the following two LC-3 instructions:0001 111 010 0 00 0111010 010 110011110If the source operands are located in memory, also distinguish the addressing mode used to access that memory. from memory using Base+Offset adressing mode immediately from the instruction's address Correct! directly from a register Correct Answer from memory using Indirect addressing mode You Answered from memory using PC-Relative addressing mode immediately from the instruction
NOT 1 0 0 1 DST SRC 1 1 1 1 1 1 R[DST] ← NOT(R[SRC])ADD 0 0 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] + R[SRC2]AND 0 1 0 1 DST SRC1 0 0 0 SRC2 R[DST] ← R[SRC1] & R[SRC2]ADD 0 0 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] + SEXT(Immediate)AND 0 1 0 1 DST SRC 1 Immediate R[DST] ← R[SRC] & SEXT(Immediate)LDR 0 1 1 0 DST BASE Offset R[DST] ← M[R[BASE]+SEXT(Offset)]STR 0 1 1 1 SRC BASE Offset M[R[BASE]+SEXT(Offset)] ← R[SRC]LD 0 0 1 0 DST PC Offset R[DST] ← M[inc(PC)+SEXT(PCOffset)]ST 0 0 1 1 SRC PC Offset M[inc(PC)+SEXT(PCOffset)] ← R[SRC]LDI 1 0 1 0 DST PC Offset R[DST] ← M[M[inc(PC)+SEXT(PCOffset)]]STI 1 0 1 1 SRC PC Offset M[M[inc(PC)+SEXT(PCOffset)]] ← R[SRC]LEA 1 1 1 0 DST PC Offset R[DST] ← inc(PC)+SEXT(PCOffset)BR 0 0 0 0 N Z P PC Offset PC ← inc(PC)+SEXT(PCOffset) if condition is trueelse PC ← inc(PC), see Note 3 below.JMP 1 1 0 0 0 0 0 BASE 0 0 0 0 0 0 PC ← R[BASE]TRAP 1 1 1 1 0 0 0 0 Trap Vector jump to trap vector, see Note 4 below.UNUSED 1 1 0 1 invalid instructionNotes:BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]Immediate (5), Offset (6), PC Offset (9) are N-bit 2's complement integers, where N is given in ()'sCondition Codesare set by ADD, AND, NOT, LD, LDR, LDI, LEAare used by BR based on the most recent instruction to set CCTrap Vector is an 8-bit value that is used to call an OS service routine:0x21 output a character0x23 input a character0x25 halt the program Flag question: Question 3Question 310 ptsAssume the following shows the contents of memory locations:ADDRESS CONTENTS0x3020 0000 0000 0000 01010x3021 0000 0000 0000 10100x3022 0000 0000 0000 01000x3023 0000 0000 0000 10110x3024 0000 0000 0000 00110x3025 0000 0000 0000 1100The machine program below adds some of the integers in the memory shown above. Which ones and in what order depends on the details of the machine instructions.0x3000 1110 001 0000111110x3001 0101 011 011 1 000000x3002 0101 010 010 1 000000x3003 0001 010 010 1 000110x3004 0000 010 0000001010x3005 0110 100 001 0000010x3006 0001 011 011 0 00 1000x3007 0001 001 001 1 000010x3008 0001 010 010 1 111110x3009 0000 111 1111110100x300A 1111 0000 0010 0101Your task is to carefully trace the execution of the machine instructions above to determine the consecutive changes to R3.(Enter your 16-bit answers in hex like the following example: 0x2A3F)A.) What is the first value assigned to R3 by the instructions above? B.) What is the second value assigned to R3 by the instructions above? C.) What is the third value assigned to R3 by the instructions above? D.) What is the fourth value assigned to R3 by the instructions above?
If R1 contains xFFFF and R2 contains x0000 then what are the condition code values after the following instruction is executed?0101 011 001 0 00 010A.) N is B.) Z is C.) P is D.) Is it possible for more than one condition code in LC-3 to be set to 1 at the same time?
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