Observe the sequential circuit in Fig. 1. Which of the following is a possible correct waveform of the output? All used D flip-flops are positive edge triggered, Q0 is initially PRESET and Q1 CLEARED.

Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be

Which of the following is correct for a gated D-type flip-flop?*The Q output is either SET or RESET as soon as the D input goes HIGH or LOWThe output complement follows the input when enabledOnly one of the inputs can be HIGH at a timeThe output toggles if one of the inputs is held HIGH

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________*The clock pulse is

Consider the sequential circuit in the following figure with four 4-bitregisters (made of rising edge sensitive D flip-flops):The initial values in the registers are the following integers:Register A = 8Register B = 4Register C = 1Register D = 5What are the values of the register B after 7 raising edges in the clock?

The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?