The hardware-software interface, embodied in the instruction set architecture (ISA), isarguably the most important interface in a computer system. Yet, in contrast to nearly allother interfaces in a modern computer system, all commercially popular ISAs are proprietary.A free and open ISA standard has the potential to increase innovation in microprocessordesign, reduce computer system cost, and, as Moore’s law wanes, ease the transition to morespecialized computational devices.In this dissertation, I present the RISC-V instruction set architecture. RISC-V is a freeand open ISA that, with three decades of hindsight, builds and improves upon the originalReduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISAwith a variety of optional extensions. The base ISA is very simple, making RISC-V suitablefor research and education, but complete enough to be a suitable ISA for inexpensive, low-power embedded devices. The optional extensions form a more powerful ISA for general-purpose and high-performance computing. I also present and evaluate a new RISC-V ISAextension for reduced code size, which makes RISC-V more compact than all popular 64-bitISAs.

This text is a summary of a dissertation on the RISC-V instruction set architecture (ISA). The author argues that the hardware-software interface, embodied in the ISA, is the most important interface in a computer system. However, unlike most other interfaces in a modern computer system, all commercially popular ISAs are proprietary. The author suggests that a free and open ISA standard could increase innovation in microprocessor design, reduce computer system cost, and ease the transition to more specialized computational devices as Moore’s law wanes.

The RISC-V ISA is presented as a free and open ISA that builds and improves upon the original Reduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISA with a variety of optional extensions. The base ISA is simple, making RISC-V suitable for research and education, but also complete enough to be a suitable ISA for inexpensive, low-power embedded devices. The optional extensions form a more powerful ISA for general-purpose and high-performance computing. The author also presents and evaluates a new RISC-V ISA extension for reduced code size, which makes RISC-V more compact than all popular 64-bit ISAs.