If the CPU fails to find the page number in the TLB (20 nanoseconds), then it must first access memory for the page table and frame number (100 nanoseconds) in cache memory, and then access the desired byte in main memory (100 nanoseconds), for a total of 220 nanoseconds. Find the effective memory-access time if hit ratio is 80%:Here TLB is a buffer, that additionally is associated with Cache space140 nanoseconds160 nanoseconds120 nanoseconds130 nanoseconds

If the average time to handle a page fault is 10 milliseconds, and a memory access requires 1 microsecond, then achieving a 99.99% hit ratio would lead to an average memory access time ofa.1 millisecondb.1.9999 millisecondsc.1.9999 microsecondsd.9.999 microseconds

A small computer has a direct-mapped data cache of size 1 kilo Bytes. lts block size is 32 bytes, hit time is 2 processor clock cycles, and, the miss penalty is 20 processor clock cyclesWhile running a loop, in each iteration data (of size 1 byte) is accessed from memory addresses 6, 522, 768, 1028. If the loop iterates 10 times, compute the average data access time for the loop.

The sequence of pages which are to be referred by microprocessor is as follows:D,C,B,A,D,C,E,D,C,B,A,BThe number of page faults that will occur in the algorithm LRU with three page frames will beSelect one:a. 9b. 10c. 8d. 7

A program uses 1600 instructions. Microprocessor references cache memory for 1493 instructions with ZERO wait states. Each main memory reference requires 3 WAIT states. Calculate the miss rate in the system. Select one:a. 92.33 %b. 6.67 %c. 7.67%d. 93.33 %

Consider a 32-bit processor that uses a direct-mapped cache with a total capacity of 2KB with 64B cache blocks. Reminder: K = 210The table below provides a list of memory address that a program accesses, where the top address is accessed first. Assume the cache is initially empty, so that the first access is a miss. Which of these accesses result in a cache hit?