What statement below is incorrect?a.MDR is connected to the data bus.b.MAR is "the only way" for the CPU to communicate with data bus.c.fetch and store are two key operations on memory.d.MAR is connected to the address bus.

The Memory Data Register (MDR) is designed such that it _____.a.is physically connected to each cell in memoryb.is logically connected to all registersc.can be activated by the program counterd.is effectively connected to every cell in the memory unit

If the instruction involves reading from or writing to memory, the __________ register will be used to hold the address, and the __________ register will hold the data to be written or read.  PC and DRIMAR and IRMAR and MDRMAR and DATA BusALU and DR

The control signals that orchestrate the entire fetch-decode-execute cycle are generated by the __________ and is transmitted through___________________CPU and Control BusCU and Data BusCU and Control BusCPU and Data Bus

The CPU contains three buses; the control bus, the address bus and the data bus. What is a bus? What is the purpose of each bus in terms of the fetch-execute cycle?

A memory address register (MAR), which specifies the address in memory for the next read or write; and a memory buffer register (MBR), which contains the data to be written into memory or which receives the data read from memory.Group of answer choicesTrueFalse