Which of the following is a superset of Verilog?a.System VHDLb.VHDLc.Verilogd.System Verilog

Which of the following is true about parameters?a.All of the aboveb.Parameters enable Verilog code to be compatible with VHDLc.Parameters cannot accept a default valued.The default size of a parameter in most synthesizers is the size of an integer, 32 bits

Which logic level is not supported by Verilog?0ZXU

Which of the following loops are supported by verilog?a.if-else loopb.for loopc.All the aboved.while loop

What is Veriloga.A data visualization toolb.A high-level programming language for software developmentc.A programming language for hardware description.d.An operating system

Draw the logic circuits for below Verilog code snippets.Question 1.always @ (posedge clock)beginq1=m;q2=q1;endQuestion 2.always @ (posedge clock)beginq2=q1;q1=m;end