Assume that the arbiter has request inputs and acknowledge outputs. The write_data[31:0] signals that are passed onto the SRAM_Controller module do not depend on the acknowledge outputs of the arbiter.Question 9Select one:TrueFalse

During the SRAM write cycle all outputs of the SRAM_Controller module to the SRAM are a combinational logic function made up of one or more of the bus bridge signals: bus_enable, rw, address and byte_enable.Question 3Select one:TrueFalse

The SRAM controller module logic needed to be updated in order to complete the second part of this lab exercise.Question 10Select one:TrueFalse

During an SRAM read cycle, the SRAM_DQ signals are driven by the FPGA with read_data.Question 7Select one:TrueFalse

What signals does the SRAM_UB_N depend on in the SRAM_Controller module? Question 6Select one: a. stage state variable, byte_enable[2], byte_enable[1] b. stage state variable, byte_enable[3], byte_enable[1] c. stage state variable, byte_enable[3], byte_enable[2] d. byte_enable[2], byte_enable[0] e. byte_enable[3], byte_enable[0]

What signals does the SRAM_UB_N depend on in the SRAM_Controller module?Question 6Select one:a.stage state variable, byte_enable[2], byte_enable[1]b.stage state variable, byte_enable[3], byte_enable[1]c.stage state variable, byte_enable[3], byte_enable[2]d.byte_enable[2], byte_enable[0]e.byte_enable[3], byte_enable[0]