What is a Makefile?

A Makefile is a file containing a set of directives used by a make build automation tool to generate a target/goal. The make utility requires a file, Makefile (or makefile), which defines set of tasks to be executed. You might have a few C files in a directory and you want to compile them to create the executable named myexe.

Here's a step-by-step explanation:

1. A Makefile typically starts with some variable definitions which are then followed by a set of rules. Variables are just like variables in any programming language. They are just placeholders which are filled in at the time of execution.

2. Rules are made up of three parts: a target, a list of dependencies and a command, like so:

target: dependencies 
[tab] system command

3. The target is the object file (.o file) that the rule makes. The dependencies are files that must exist before the rule is run. The system command is a command that is run in the shell.

4. The make program reads the makefile and executes the rule only if the target file is older than the source file or if the target file does not exist.

5. If you have multiple C files and you want to compile them to create one executable, you can define a rule for each C file and then you can define one rule to create the final executable linking all the object files together.

6. The make utility will ensure a minimal number of commands are executed. For example, if you have 10 C files and you change one, then only that file is compiled to create the object file and then finally the executable is linked with this new object file and the rest of the untouched object files.

In summary, a Makefile automates the compiling process, reducing the risk of human errors while compiling and linking the source files.