Design and develop an instruction pipeline working under various situationsof pipeline stall

Instruction execution throughput increases in proportion with the number of pipeline stages

For a six-stage pipelining, the initial instruction requires-------cycle for execution

The performance of a pipelined processor suffers if (1 Point)The pipeline stages have different- delays.Consecutive instructions are depended- on each other.The pipeline stages share hardware resources.All of the above

A program having 10 instructions (without Branch and Call instructions) is executedon non-pipeline and pipeline processors. All instructions are of same length andhaving 4 pipeline stages and time required to each stage is 1nsec. (Assume thefour stages as Fetch Instruction ,Decode Instruction, Execute Instruction, WriteOutput)i.) Calculate time required to execute the program on Non-pipeline and Pipelineprocessor.ii) Show the pipeline processor with a diagram

Explain the concept of pipelining in microprocessor design and how it contributesto improving performance. Discuss any potential drawbacks of pipelining.